The present invention relates generally to semiconductors, and more specifically the invention pertains to a device and method to minimize current leakage between adjacent sections of a semiconductor device, while minimizing topographic variations.
Advanced semiconductor devices have increasingly complex layouts, which often include multiple contacts to allow sections of the device to be independently controlled. Some form of electrical isolation between these sections is desirable, or even necessary, in many cases. While integrated circuits often use ion implants for such isolation, this is often not desirable for the small-scale production typically done with semiconductor lasers, due to the difficulty and expense of ion implantation. The simplest method of electrically isolating multiple contacts is to etch the contact layers (usually p-type) that connect them. In most cases, forming v-grooves by wet etching is the simplest form of etching. (Dry etching may also be used, but etch damage typically results in lower reverse breakdown voltage, and higher leakage currents.) For semiconductor laser devices, wet-etched v-grooves have the added benefit of suppressing parasitic lasing across the laser which often happens in wide lasers without v-grooves.
Unfortunately, the most straight-forward designs for v-groove patterns carry with them (unanticipated) negative consequences. Most notably, when combined with the widely-used self-aligned contact schemes (which rely on photoresist planarization and uniform etch back to expose only the tops of the ridge waveguides), standard designs prove very difficult to implement. More generally, maintaining device planarity is important for a wide variety of integrated electronic applications, due to the difficulty in obtaining step coverage in non-planar wafers.
The task of minimizing leakage of current between adjacent sections of semiconductors is alleviated, to some extent, by the systems disclosed in the following U.S. Patents, the disclosures of which are incorporated herein by reference:
U.S. Pat. No. 4,992,137 issued to Cathey, et al; PA1 U.S. Pat. No. 4,969,712 issued to Westwood, et al; PA1 U.S. Pat. No. 4,911,784 issued to Hensel, et al; PA1 U.S. Pat. No. 4,759,823 issued to Asselanis et al;
The patents to Cathey et al, Westwood et al, Hensel et al, and Asselanis et al disclose etching on semiconductors but do not disclose shapes. While these references are instructive, a need remains to improve device planarity wherever etched trenches are needed (e.g., to spoil parasitic lasing, or for electrical isolation). The present invention is intended to satisfy that need.